Information

Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The peripheral bridge (AIPS-Lite) converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
The peripheral bridge supports up to 128 peripherals. The bridge includes separate clock
enable inputs for each of the slots to accommodate slower peripherals.
19.1.1 Features
Key features of the peripheral bridge are:
• Supports up to 128 peripherals and two global external peripheral spaces
• Supports 8-, 16-, and 32-bit width peripheral slots
• Allows each independently configurable peripheral to include a clock enable, which
allows peripherals to operate at any speed less than the system clock rate.
• Provides programming model provides memory protection functionality
19.1.2 General operation
The peripherals connected to the peripheral bridge are modules that contain readable/
writable control and status registers. The system masters read and write these registers
through the peripheral bridge. The peripheral bridge generates the following as inputs to
the peripherals:
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 319