Information

DMAMUX memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_1004 Channel Configuration register (DMAMUX0_CHCFG4) 8 R/W 00h 20.3.1/324
4002_1005 Channel Configuration register (DMAMUX0_CHCFG5) 8 R/W 00h 20.3.1/324
4002_1006 Channel Configuration register (DMAMUX0_CHCFG6) 8 R/W 00h 20.3.1/324
4002_1007 Channel Configuration register (DMAMUX0_CHCFG7) 8 R/W 00h 20.3.1/324
4002_1008 Channel Configuration register (DMAMUX0_CHCFG8) 8 R/W 00h 20.3.1/324
4002_1009 Channel Configuration register (DMAMUX0_CHCFG9) 8 R/W 00h 20.3.1/324
4002_100A Channel Configuration register (DMAMUX0_CHCFG10) 8 R/W 00h 20.3.1/324
4002_100B Channel Configuration register (DMAMUX0_CHCFG11) 8 R/W 00h 20.3.1/324
4002_100C Channel Configuration register (DMAMUX0_CHCFG12) 8 R/W 00h 20.3.1/324
4002_100D Channel Configuration register (DMAMUX0_CHCFG13) 8 R/W 00h 20.3.1/324
4002_100E Channel Configuration register (DMAMUX0_CHCFG14) 8 R/W 00h 20.3.1/324
4002_100F Channel Configuration register (DMAMUX0_CHCFG15) 8 R/W 00h 20.3.1/324
20.3.1 Channel Configuration register (DMAMUXx_CHCFGn)
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same Source value
will result in unpredictable behavior.
NOTE
Before changing the trigger or source settings a DMA channel
must be disabled via the CHCFGn[ENBL] bit.
Addresses: 4002_1000h base + 0h offset + (1d × n), where n = 0d to 15d
Bit 7 6 5 4 3 2 1 0
Read
ENBL TRIG SOURCE
Write
Reset
0 0 0 0 0 0 0 0
DMAMUXx_CHCFGn field descriptions
Field Description
7
ENBL
DMA Channel Enable
Enables the DMA channel.
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
324 Freescale Semiconductor, Inc.