Information

DMAMUXx_CHCFGn field descriptions (continued)
Field Description
0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA
has separate channel enables/disables, which should be used to disable or re-configure a DMA
channel.
1 DMA channel is enabled
6
TRIG
DMA Channel Trigger Enable
Enables the periodic trigger capability for the triggered DMA channel.
0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply
route the specified source to the DMA channel. (Normal mode)
1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic
Trigger mode.
5–0
SOURCE
DMA Channel Source (Slot)
Specifies which DMA source, if any, is routed to a particular DMA channel. See your device's chip
configuration details for further details about the peripherals and their slot numbers.
20.4 Functional description
The primary purpose of the DMA MUX is to provide flexibility in the system's use of the
available DMA channels. As such, configuration of the DMA MUX is intended to be a
static procedure done during execution of the system boot code. However, if the
procedure outlined in Enabling and configuring sources is followed, the configuration of
the DMA MUX may be changed during the normal operation of the system.
Functionally, the DMA MUX channels may be divided into two classes:
• Channels which implement the normal routing functionality plus periodic triggering
capability
• Channels which implement only the normal routing functionality
20.4.1 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first four channels of the DMA MUX
provide a special periodic triggering capability that can be used to provide an automatic
mechanism to transmit bytes, frames, or packets at fixed intervals without the need for
processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as
such, the configuration of the periodic triggering interval is done via configuration
registers in the PIT. See the section on periodic interrupt timer for more information on
this topic.
Chapter 20 Direct Memory Access Multiplexer (DMAMUX)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 325