Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_801E Clear Error Register (DMA_CERR) 8
W
(always
reads
zero)
00h
21.3.11/
354
4000_801F Clear Interrupt Request Register (DMA_CINT) 8
W
(always
reads
zero)
00h
21.3.12/
355
4000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h
21.3.13/
355
4000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h
21.3.14/
357
4000_8034 Hardware Request Status Register (DMA_HRS) 32 R/W 0000_0000h
21.3.15/
358
4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W Undefined
21.3.16/
359
4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W Undefined
21.3.16/
359
4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W Undefined
21.3.16/
359
4000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W Undefined
21.3.16/
359
4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined
21.3.17/
360
4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined
21.3.18/
360
4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined
21.3.19/
361
4000_9008
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD0_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
362
4000_9008
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD0_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
363
4000_9008
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD0_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
364
4000_900C
TCD Last Source Address Adjustment
(DMA_TCD0_SLAST)
32 R/W Undefined
21.3.23/
365
4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined
21.3.24/
365
4000_9014
TCD Signed Destination Address Offset
(DMA_TCD0_DOFF)
16 R/W Undefined
21.3.25/
366
4000_9016
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD0_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
367
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 339