Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined
21.3.27/
368
4000_9018
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD0_DLASTSGA)
32 R/W Undefined
21.3.28/
369
4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined
21.3.29/
370
4000_901E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD0_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
372
4000_901E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD0_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
373
4000_9020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined
21.3.17/
360
4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined
21.3.18/
360
4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined
21.3.19/
361
4000_9028
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD1_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
362
4000_9028
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
363
4000_9028
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD1_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
364
4000_902C
TCD Last Source Address Adjustment
(DMA_TCD1_SLAST)
32 R/W Undefined
21.3.23/
365
4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined
21.3.24/
365
4000_9034
TCD Signed Destination Address Offset
(DMA_TCD1_DOFF)
16 R/W Undefined
21.3.25/
366
4000_9036
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD1_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
367
4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined
21.3.27/
368
4000_9038
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD1_DLASTSGA)
32 R/W Undefined
21.3.28/
369
4000_903C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined
21.3.29/
370
4000_903E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD1_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
372
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
340 Freescale Semiconductor, Inc.