Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9068
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD3_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
362
4000_9068
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
363
4000_9068
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD3_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
364
4000_906C
TCD Last Source Address Adjustment
(DMA_TCD3_SLAST)
32 R/W Undefined
21.3.23/
365
4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined
21.3.24/
365
4000_9074
TCD Signed Destination Address Offset
(DMA_TCD3_DOFF)
16 R/W Undefined
21.3.25/
366
4000_9076
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD3_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
367
4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined
21.3.27/
368
4000_9078
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD3_DLASTSGA)
32 R/W Undefined
21.3.28/
369
4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined
21.3.29/
370
4000_907E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD3_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
372
4000_907E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD3_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
373
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD4_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
372
21.3.1 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through without regard to priority.
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
342 Freescale Semiconductor, Inc.