Information

DMA_ES field descriptions (continued)
Field Description
TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or
TCDn_CITER[CITER] is equal to zero, or
TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
2
SGE
Scatter/Gather Configuration Error
0 No scatter/gather configuration error
1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
checked at the beginning of a scatter/gather operation after major loop completion if
TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1
SBE
Source Bus Error
0 No source bus error
1 The last recorded error was a bus error on a source read
0
DBE
Destination Bus Error
0 No destination bus error
1 The last recorded error was a bus error on a destination write
21.3.3 Enable Request Register (DMA_ERQ)
The ERQ register provides a bit map for the 4 implemented channels to enable the
request signal for each channel. The state of any given channel enable is directly affected
by writes to this register; it is also affected by writes to the SERQ and CERQ. The
{S,C}ERQ registers are provided so the request enable for a single channel can easily be
modified without needing to perform a read-modify-write sequence to the ERQ.
DMA request input signals and this enable request flag must be asserted before a
channel’s hardware service request is accepted. The state of the DMA enable request flag
does not affect a channel service request made explicitly through software or a linked
channel request.
Address: DMA_ERQ is 4000_8000h base + Ch offset = 4000_800Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ERQ3
ERQ2
ERQ1
ERQ0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_ERQ field descriptions
Field Description
31–4
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
346 Freescale Semiconductor, Inc.