Information

DMA_HRS field descriptions (continued)
Field Description
1
HRS1
Hardware Request Status Channel 1
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
0
HRS0
Hardware Request Status Channel 0
0 A hardware service request for the corresponding channel is not present
1 A hardware service request for the corresponding channel is present
21.3.16 Channel n Priority Register (DMA_DCHPRIn)
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel. The channel priorities
are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next
priority, then 2, then 3. Software must program the channel priorities with unique values.
Otherwise, a configuration error is reported. The range of the priority value is limited to
the values of 0 through 3.
Addresses: DCHPRI3 is 4000_8000h base + 100h offset = 4000_8100h
DCHPRI2 is 4000_8000h base + 101h offset = 4000_8101h
DCHPRI1 is 4000_8000h base + 102h offset = 4000_8102h
DCHPRI0 is 4000_8000h base + 103h offset = 4000_8103h
Bit 7 6 5 4 3 2 1 0
Read
ECP DPA
0
CHPRI
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_DCHPRIn field descriptions
Field Description
7
ECP
Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority channel’s service request
1 Channel n can be temporarily suspended by the service request of a higher priority channel
6
DPA
Disable Preempt Ability
0 Channel n can suspend a lower priority channel
1 Channel n cannot suspend any channel, regardless of channel priority
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 359