Information

DMA_DCHPRIn field descriptions (continued)
Field Description
5–2
Reserved
This read-only field is reserved and always has the value zero.
1–0
CHPRI
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number
for each priority register, i.e., DCHPRI3[CHPRI] equals 0b11.
21.3.17 TCD Source Address (DMA_TCD_SADDR)
Addresses: TCD0_SADDR is 4000_8000h base + 1000h offset = 4000_9000h
TCD1_SADDR is 4000_8000h base + 1020h offset = 4000_9020h
TCD2_SADDR is 4000_8000h base + 1040h offset = 4000_9040h
TCD3_SADDR is 4000_8000h base + 1060h offset = 4000_9060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SADDR
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_SADDR field descriptions
Field Description
31–0
SADDR
Source Address
Memory address pointing to the source data.
21.3.18 TCD Signed Source Address Offset (DMA_TCD_SOFF)
Addresses: TCD0_SOFF is 4000_8000h base + 1004h offset = 4000_9004h
TCD1_SOFF is 4000_8000h base + 1024h offset = 4000_9024h
TCD2_SOFF is 4000_8000h base + 1044h offset = 4000_9044h
TCD3_SOFF is 4000_8000h base + 1064h offset = 4000_9064h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
SOFF
Write
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
360 Freescale Semiconductor, Inc.