Information

DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued)
Field Description
preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
21.3.23 TCD Last Source Address Adjustment (DMA_TCD_SLAST)
Addresses: TCD0_SLAST is 4000_8000h base + 100Ch offset = 4000_900Ch
TCD1_SLAST is 4000_8000h base + 102Ch offset = 4000_902Ch
TCD2_SLAST is 4000_8000h base + 104Ch offset = 4000_904Ch
TCD3_SLAST is 4000_8000h base + 106Ch offset = 4000_906Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLAST
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_SLAST field descriptions
Field Description
31–0
SLAST
Last source Address Adjustment
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
21.3.24 TCD Destination Address (DMA_TCD_DADDR)
Addresses: TCD0_DADDR is 4000_8000h base + 1010h offset = 4000_9010h
TCD1_DADDR is 4000_8000h base + 1030h offset = 4000_9030h
TCD2_DADDR is 4000_8000h base + 1050h offset = 4000_9050h
TCD3_DADDR is 4000_8000h base + 1070h offset = 4000_9070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DADDR
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 365