Information

Section Number Title Page
43.4.7 Interrupts/DMA requests..............................................................................................................................998
43.4.8 Power saving features..................................................................................................................................1000
43.5 Initialization/application information...........................................................................................................................1001
43.5.1 How to manage DSPI queues.......................................................................................................................1001
43.5.2 Switching Master and Slave mode...............................................................................................................1002
43.5.3 Initializing DSPI in Master/Slave Modes....................................................................................................1003
43.5.4 Baud rate settings.........................................................................................................................................1003
43.5.5 Delay settings...............................................................................................................................................1004
43.5.6 Calculation of FIFO pointer addresses.........................................................................................................1005
Chapter 44
Inter-Integrated Circuit (I2C)
44.1 Introduction...................................................................................................................................................................1009
44.1.1 Features........................................................................................................................................................1009
44.1.2 Modes of operation......................................................................................................................................1010
44.1.3 Block diagram..............................................................................................................................................1010
44.2 I2C signal descriptions..................................................................................................................................................1011
44.3 Memory map and register descriptions.........................................................................................................................1011
44.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................1012
44.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................1013
44.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................1014
44.3.4 I2C Status register (I2Cx_S)........................................................................................................................1016
44.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................1017
44.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................1018
44.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................1019
44.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1020
44.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1020
44.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1022
44.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1022
44.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1023
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 37