Information

21.3.29 TCD Control and Status (DMA_TCD_CSR)
Addresses: TCD0_CSR is 4000_8000h base + 101Ch offset = 4000_901Ch
TCD1_CSR is 4000_8000h base + 103Ch offset = 4000_903Ch
TCD2_CSR is 4000_8000h base + 105Ch offset = 4000_905Ch
TCD3_CSR is 4000_8000h base + 107Ch offset = 4000_907Ch
Bit 15 14 13 12 11 10 9 8
Read
BWC
0
MAJORLINKCH
Write
Reset
x* x* x* x* x* x* x* x*
Bit
7 6 5 4 3 2 1 0
Read
DONE ACTIVE
MAJORELINK
ESG DREQ INTHALF INTMAJOR START
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_CSR field descriptions
Field Description
15–14
BWC
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for 4 cycles after each r/w
11 eDMA engine stalls for 8 cycles after each r/w
13–10
Reserved
This read-only field is reserved and always has the value zero.
9–8
MAJORLINKCH
Link Channel Number
If (MAJORELINK = 0) then
• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.
else
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit.
7
DONE
Channel Done
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
370 Freescale Semiconductor, Inc.