Information

WDOG_TMROUTL field descriptions
Field Description
15–0
TIMEROUTLOW
Shows the value of the lower 16 bits of the watchdog timer.
23.7.11 Watchdog Reset Count register (WDOG_RSTCNT)
Address: WDOG_RSTCNT is 4005_2000h base + 14h offset = 4005_2014h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
RSTCNT
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WDOG_RSTCNT field descriptions
Field Description
15–0
RSTCNT
Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing
1 to the bit to be cleared enables you to clear the contents of this register.
23.7.12 Watchdog Prescaler register (WDOG_PRESC)
Address: WDOG_PRESC is 4005_2000h base + 16h offset = 4005_2016h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0
PRESCVAL
0
Write
Reset
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
WDOG_PRESC field descriptions
Field Description
15–11
Reserved
This read-only field is reserved and always has the value zero.
10–8
PRESCVAL
3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG
clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK.
7–0
Reserved
This read-only field is reserved and always has the value zero.
23.8 Watchdog operation with 8-bit access
Watchdog operation with 8-bit access
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
424 Freescale Semiconductor, Inc.