Information

• WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this
means that even after the close of the WCT window, you have to wait for the
synchronized system reset to deassert in the watchdog clock domain, before
expecting the configuration updates to take effect.
• The time-out value of the watchdog should be set to a minimum of four watchdog
clock cycles. This is to take into account the delay in new settings taking effect in the
watchdog clock domain.
• You must take care not only to refresh the watchdog within the watchdog timer's
actual time-out period, but also provide enough allowance for the time it takes for the
refresh sequence to be detected by the watchdog timer, on the watchdog clock.
• Updates cannot be made in the bus clock cycle immediately following the write of
the unlock sequence, but one bus clock cycle later.
• It should be ensured that the time-out value for the watchdog is always greater than
2xWCT time + 20 bus clock cycles.
• An attempted refresh operation, in between the two writes of the unlock sequence
and in the WCT time following a successful unlock, will go undetected.
• Trying to unlock the watchdog within the WCT time after an initial unlock has no
effect.
• The refresh and unlock operations and interrupt are not automatically disabled in the
watchdog functional test mode.
• After emerging from a reset due to a watchdog functional test, you are still expected
to go through the mandatory steps of unlocking and configuring the watchdog. The
watchdog continues to be in its functional test mode and therefore you should pull
the watchdog out of the functional test mode within WCT time of reset.
• After emerging from a reset due to a watchdog functional test, you still need to go
through the mandatory steps of unlocking and configuring the watchdog.
• You must ensure that both the clock inputs to the glitchless clock multiplexers are
alive during the switching of clocks. Failure to do so results in a loss of clock at their
outputs.
• There is a gap of two to three watchdog clock cycles from the point that stop mode is
entered to the watchdog timer actually pausing, due to synchronization. The same
holds true for an exit from the stop mode, this time resulting in a two to three
Chapter 23 Watchdog Timer (WDOG)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 427