Information

Section Number Title Page
48.9 TSI module initialization..............................................................................................................................................1212
48.9.1 Initialization Sequence.................................................................................................................................1213
Chapter 49
JTAG Controller (JTAGC)
49.1 Introduction...................................................................................................................................................................1215
49.1.1 Block diagram..............................................................................................................................................1215
49.1.2 Features........................................................................................................................................................1216
49.1.3 Modes of operation......................................................................................................................................1216
49.2 External signal description............................................................................................................................................1218
49.2.1 TCK—Test clock input................................................................................................................................1218
49.2.2 TDI—Test data input...................................................................................................................................1218
49.2.3 TDO—Test data output................................................................................................................................1218
49.2.4 TMS—Test mode select...............................................................................................................................1218
49.3 Register description......................................................................................................................................................1219
49.3.1 Instruction register.......................................................................................................................................1219
49.3.2 Bypass register.............................................................................................................................................1219
49.3.3 Device identification register.......................................................................................................................1219
49.3.4 Boundary scan register.................................................................................................................................1220
49.4 Functional description...................................................................................................................................................1221
49.4.1 JTAGC reset configuration..........................................................................................................................1221
49.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port..............................................................................................1221
49.4.3 TAP controller state machine.......................................................................................................................1221
49.4.4 JTAGC block instructions............................................................................................................................1223
49.4.5 Boundary scan..............................................................................................................................................1226
49.5 Initialization/Application information..........................................................................................................................1226
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
44 Freescale Semiconductor, Inc.