Information

Table 24-16. MCG modes of operation (continued)
Mode Description
PLL Engaged External
(PEE)
PLL Engaged External (PEE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 0
• C6[PLLS] bit is written to 1
In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external
reference clock. The PLL clock frequency locks to a multiplication factor, as specified by
C6[VDIV0], times the external reference frequency, as specified by C5[PRDIV0]. The PLL's
programmable reference divider must be configured to produce a valid PLL reference clock. The
FLL is disabled in a low-power state.
PLL Bypassed External
(PBE)
PLL Bypassed External (PBE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C6[PLLS] bit is written to 1
• C2[LP] bit is written to 0
In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is
operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its
target frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock
frequency locks to a multiplication factor, as specified by its [VDIV], times the PLL reference
frequency, as specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable
reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in
a low-power state.
Bypassed Low Power
Internal (BLPI)1
Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 01
• C1[IREFS] bit is written to 1
• C6[PLLS] bit is written to 0
• C2[LP] bit is written to 1
In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and
PLL is disabled even if the C5[PLLCLKEN0] is set to 1.
Bypassed Low Power
External (BLPE)
Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C2[LP] bit is written to 1
In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is
disabled and PLL is disabled even if the C5[PLLCLKEN0] is set to 1.
Table continues on the next page...
Chapter 24 Multipurpose Clock Generator (MCG)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 449