Information

Table 24-17. MCGOUTCLK Frequency Calculation Options
(continued)
Clock Mode f
MCGOUTCLK
1
Note
FEE (FLL engaged external) (f
ext
/ FLL_R) *F f
ext
/ FLL_R must be specified for
f
fll_ref
in the appropriate device Data
Sheet
FBE (FLL bypassed external) f
ext
f
ext
/ FLL_R must be specified for
f
fll_ref
in the appropriate device Data
Sheet
FBI (FLL bypassed internal) f
int
Typical f
int
= 32 kHz
PEE (PLL engaged external) (f
ext
/ PLL_R) * M f
ext
/ PLL_R must be in the range
specified for f
pll_ref
in the appropriate
device Data Sheet
PBE (PLL bypassed external) f
ext
f
ext
/ PLL_R must be in the range
specified for f
pll_ref
in the appropriate
device Data Sheet
BLPI (Bypassed low power internal) f
int
BLPE (Bypassed low power external) f
ext
1. FLL_R is the reference divider selected by the C1[FRDIV] bits, PLL_R is the reference divider selected by C5[PRDIV0]
bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV0]
bits.
This section will include three mode switching examples using an 4 MHz external
crystal. If using an external clock source less than 2 MHz, the MCG must not be
configured for any of the PLL modes (PEE and PBE).
24.5.3.1 Example 1: Moving from FEI to PEE mode: External Crystal =
4 MHz, MCGOUTCLK frequency = 48 MHz
In this example, the MCG will move through the proper operational modes from FEI to
PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal
reference. First, the code sequence will be described. Then there is a flowchart that
illustrates the sequence.
1. First, FEI must transition to FBE mode:
a. C2 = 0x1C
• C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the
high frequency range.
• C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation.
• C2[EREFS0] set to 1, because a crystal is being used.
b. C1 = 0x90
Initialization / Application information
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
458 Freescale Semiconductor, Inc.