Information

e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired
lock.
4. Lastly, PBE mode transitions into PEE mode:
a. C1 = 0x10
• C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock
source.
b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to
feed MCGOUTCLK in the current clock mode.
• Now, with PRDIV0 of divide-by-2, and C6[VDIV0] of multiply-by-24,
MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz.
Initialization / Application information
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
460 Freescale Semiconductor, Inc.