Information

Memory map and register descriptions
The programming model consists of the FMC control registers and the program visible
cache (data and tag/valid entries).
NOTE
Program the registers only while the flash controller is idle (for
example, execute from RAM). Changing configuration settings
while a flash access is in progress can lead to non-deterministic
behavior.
Table 27-2. FMC register access
Registers Read access Write access
Mode Length Mode Length
Control registers:
PFAPR, PFB0CR
Supervisor (privileged)
mode or user mode
32 bits Supervisor (privileged)
mode only
8, 16, or 32 bits
Cache registers Supervisor (privileged)
mode or user mode
32 bits Supervisor (privileged)
mode only
32 bits
NOTE
Accesses to unimplemented registers within the FMC's address
space return a bus error.
The cache entries, both data and tag/valid, can be read at any time.
NOTE
System software is required to maintain memory coherence
when any segment of the flash cache is programmed. For
example, all buffer data associated with the reprogrammed flash
should be invalidated. Accordingly, cache program visible
writes must occur after a programming or erase event is
completed and before the new memory image is accessed.
The cache is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and
the sets are numbered 0-1. The following table elaborates on the tag/valid and data
entries.
27.4
Chapter 27 Flash Memory Controller (FMC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 485