Information

Table 27-3. Program visible cache registers
Cache
storage
Based at
offset
Contents of 32-bit read Nomenclature Nomenclature example
Tag 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way,
and y denotes the set.
TAGVDW1S1 is the 13-bit
tag and 1-bit valid for cache
entry way 1, set 1.
Data 200h Data word In DATAWxSy, x denotes the way,
and y denotes the set.
DATAW1S1 represents bits
[31:0] of data entry way 1, set
1.
FMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00F8_003Fh 27.4.1/487
4001_F004 Flash Control Register (FMC_PFB0CR) 32 R/W 3000_001Fh 27.4.2/489
4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0000_0000h 27.4.3/491
4001_F104 Cache Tag Storage (FMC_TAGVDW0S1) 32 R/W 0000_0000h 27.4.3/491
4001_F108 Cache Tag Storage (FMC_TAGVDW1S0) 32 R/W 0000_0000h 27.4.4/492
4001_F10C Cache Tag Storage (FMC_TAGVDW1S1) 32 R/W 0000_0000h 27.4.4/492
4001_F110 Cache Tag Storage (FMC_TAGVDW2S0) 32 R/W 0000_0000h 27.4.5/492
4001_F114 Cache Tag Storage (FMC_TAGVDW2S1) 32 R/W 0000_0000h 27.4.5/492
4001_F118 Cache Tag Storage (FMC_TAGVDW3S0) 32 R/W 0000_0000h 27.4.6/493
4001_F11C Cache Tag Storage (FMC_TAGVDW3S1) 32 R/W 0000_0000h 27.4.6/493
4001_F200 Cache Data Storage (FMC_DATAW0S0) 32 R/W 0000_0000h 27.4.7/494
4001_F204 Cache Data Storage (FMC_DATAW0S1) 32 R/W 0000_0000h 27.4.7/494
4001_F208 Cache Data Storage (FMC_DATAW1S0) 32 R/W 0000_0000h 27.4.8/494
4001_F20C Cache Data Storage (FMC_DATAW1S1) 32 R/W 0000_0000h 27.4.8/494
4001_F210 Cache Data Storage (FMC_DATAW2S0) 32 R/W 0000_0000h 27.4.9/495
4001_F214 Cache Data Storage (FMC_DATAW2S1) 32 R/W 0000_0000h 27.4.9/495
4001_F218 Cache Data Storage (FMC_DATAW3S0) 32 R/W 0000_0000h
27.4.10/
495
4001_F21C Cache Data Storage (FMC_DATAW3S1) 32 R/W 0000_0000h
27.4.10/
495
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
486 Freescale Semiconductor, Inc.