Information

FMC_PFB0CR field descriptions (continued)
Field Description
0 No cache way invalidation for the corresponding cache
1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
19
S_B_INV
Invalidate Prefetch Speculation Buffer
This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be
invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are
immediately cleared. This bit always reads as zero.
0 Speculation buffer and single entry buffer are not affected.
1 Invalidate (clear) speculation buffer and single entry buffer.
18–17
B0MW[1:0]
Memory Width
This read-only field defines the width of the memory.
00 32 bits
01 64 bits
1x Reserved
16
Reserved
This read-only field is reserved and always has the value zero.
15–8
Reserved
This read-only field is reserved and always has the value zero.
7–5
CRC[2:0]
Cache Replacement Control
This 3-bit field defines the replacement algorithm for accesses that are cached.
000 LRU replacement algorithm per set across all four ways
001 Reserved
010 Independent LRU with ways [0-1] for ifetches, [2-3] for data
011 Independent LRU with ways [0-2] for ifetches, [3] for data
1xx Reserved
4
B0DCE
Data Cache Enable
This bit controls whether data references are loaded into the cache.
0 Do not cache data references.
1 Cache data references.
3
B0ICE
Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
0 Do not cache instruction fetches.
1 Cache instruction fetches.
2
B0DPE
Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0 Do not prefetch in response to data references.
1 Enable prefetches in response to data references.
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
490 Freescale Semiconductor, Inc.