Information

27.4.7 Cache Data Storage (FMC_DATAW0Sn)
The cache of eight 32-bit entries is a 4-way, set-associative cache with 2 sets. The ways
are numbered 0-3 and the sets are numbered 0-1. In DATAWxSy, x denotes the way, and
y denotes the set. This section represents data for bits [31:0] of sets 0-1 in way 0.
Addresses: DATAW0S0 is 4001_F000h base + 200h offset = 4001_F200h
DATAW0S1 is 4001_F000h base + 204h offset = 4001_F204h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW0Sn field descriptions
Field Description
31–0
data[31:0]
Bits [31:0] of data entry
27.4.8 Cache Data Storage (FMC_DATAW1Sn)
The cache of eight 32-bit entries is a 4-way, set-associative cache with 2 sets. The ways
are numbered 0-3 and the sets are numbered 0-1. In DATAWxSy, x denotes the way, and
y denotes the set. This section represents data for bits [31:0] of sets 0-1 in way 1.
Addresses: DATAW1S0 is 4001_F000h base + 208h offset = 4001_F208h
DATAW1S1 is 4001_F000h base + 20Ch offset = 4001_F20Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW1Sn field descriptions
Field Description
31–0
data[31:0]
Bits [31:0] of data entry
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
494 Freescale Semiconductor, Inc.