Information

27.4.9 Cache Data Storage (FMC_DATAW2Sn)
The cache of eight 32-bit entries is a 4-way, set-associative cache with 2 sets. The ways
are numbered 0-3 and the sets are numbered 0-1. In DATAWxSy, x denotes the way, and
y denotes the set. This section represents data for bits [31:0] of sets 0-1 in way 2.
Addresses: DATAW2S0 is 4001_F000h base + 210h offset = 4001_F210h
DATAW2S1 is 4001_F000h base + 214h offset = 4001_F214h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW2Sn field descriptions
Field Description
31–0
data[31:0]
Bits [31:0] of data entry
27.4.10 Cache Data Storage (FMC_DATAW3Sn)
The cache of eight 32-bit entries is a 4-way, set-associative cache with 2 sets. The ways
are numbered 0-3 and the sets are numbered 0-1. In DATAWxSy, x denotes the way, and
y denotes the set. This section represents data for bits [31:0] of sets 0-1 in way 3.
Addresses: DATAW3S0 is 4001_F000h base + 218h offset = 4001_F218h
DATAW3S1 is 4001_F000h base + 21Ch offset = 4001_F21Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW3Sn field descriptions
Field Description
31–0
data[31:0]
Bits [31:0] of data entry
Chapter 27 Flash Memory Controller (FMC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 495