Information

27.5 Functional description
The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides
managing the interface between the device and the flash memory and FlexMemory, the
FMC can be used to restrict access from crossbar switch masters and customize the cache
and buffers to provide single-cycle system-clock data-access times. Whenever a hit
occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the
requested data is transferred within a single system clock.
Upon system reset, the FMC is configured to provide a significant level of buffering for
transfers from the flash memory or FlexMemory:
• Crossbar masters 0, 1, 2 have read access to the memory.
• When FlexNVM is used with FlexRAM as EEPROM, these crossbar masters have
write access to the EEPROM.
• Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2.
• The cache is configured for least recently used (LRU) replacement for all four ways.
• The cache is configured for data or instruction replacement.
• The single-entry buffer is enabled.
Though the default configuration provides a high degree of flash acceleration, advanced
users may desire to customize the FMC buffer configurations to maximize throughput for
their use cases. When reconfiguring the FMC for custom use cases, do not program the
FMC's control registers while the flash memory or FlexMemory is being accessed.
Instead, change the control registers with a routine executing from RAM in supervisor
mode.
The FMC's cache and buffering controls within PFB0CR allow the tuning of resources to
suit particular applications' needs. The cache and two buffers are each controlled
individually. The register controls enable buffering and prefetching per access type
(instruction fetch or data reference). The cache also supports three types of LRU
replacement algorithms:
• LRU per set across all four ways,
• LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and
• LRU with ways [0-2] for instruction fetches and way [3] for data fetches.
As an application example: if both instruction fetches and data references are accessing
the flash memory, control is available to send instruction fetches, data references, or both
to the cache or the single-entry buffer. Likewise, speculation can be enabled or disabled
for either type of access. If both instruction fetches and data references are cached, the
cache's way resources may be divided in several ways between the instruction fetches and
data references.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
496 Freescale Semiconductor, Inc.