Information

Address: FTFL_FCNFG is 4002_0000h base + 1h offset = 4002_0001h
Bit 7 6 5 4 3 2 1 0
Read
CCIE RDCOLLIE
ERSAREQ
ERSSUSP
0 PFLSH RAMRDY EEERDY
Write
Reset
0 0 0 0 0 0 0 0
FTFL_FCNFG field descriptions
Field Description
7
CCIE
Command Complete Interrupt Enable
The CCIE bit controls interrupt generation when a flash command completes.
0 Command complete interrupt disabled
1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF]
flag is set.
6
RDCOLLIE
Read Collision Error Interrupt Enable
The RDCOLLIE bit controls interrupt generation when a flash memory read collision error occurs.
0 Read collision error interrupt disabled
1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory
read collision error is detected (see the description of FSTAT[RDCOLERR]).
5
ERSAREQ
Erase All Request
This bit issues a request to the memory controller to execute the Erase All Blocks command and release
security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip
Configuration details on how to request this command.
The ERSAREQ bit sets when an erase all request is triggered external to the flash memory module and
CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module
when the operation completes.
0 No request or request complete
1 Request to:
1. run the Erase All Blocks command,
2. verify the erased state,
3. program the security byte in the Flash Configuration Field to the unsecure state, and
4. release MCU security by setting the FSEC[SEC] field to the unsecure state.
4
ERSSUSP
Erase Suspend
The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is
executing.
0 No suspend requested
1 Suspend the current Erase Flash Sector command execution.
3
Reserved
This read-only field is reserved and always has the value zero.
2
PFLSH
Flash memory configuration
0 Flash memory module configured for FlexMemory that supports data flash and/or EEPROM
1 Reserved
1
RAMRDY
RAM Ready
This flag indicates the current status of the FlexRAM .
Table continues on the next page...
Memory Map and Registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
510 Freescale Semiconductor, Inc.