Information

FTFL_FSEC field descriptions (continued)
Field Description
01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
10 Backdoor key access enabled
11 Backdoor key access disabled
5–4
MEEN
Mass Erase Enable Bits
Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is
only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is
set to unsecure, the MEEN setting does not matter.
00 Mass erase is enabled
01 Mass erase is enabled
10 Mass erase is disabled
11 Mass erase is enabled
3–2
FSLACC
Freescale Failure Analysis Access Code
These bits enable or disable access to the flash memory contents during returned part failure analysis at
Freescale. When SEC is secure and FSLACC is denied, access to the program flash contents is denied
and any failure analysis performed by Freescale factory test must begin with a full erase to unsecure the
part.
When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), Freescale factory
testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when the
SEC bits are set to secure. When the SEC field is set to unsecure, the FSLACC setting does not matter.
00 Freescale factory access granted
01 Freescale factory access denied
10 Freescale factory access denied
11 Freescale factory access granted
1–0
SEC
Flash Security
These bits define the security state of the MCU. In the secure state, the MCU limits access to flash
memory module resources. The limitations are defined per device and are detailed in the Chip
Configuration details. If the flash memory module is unsecured using backdoor key access, the SEC bits
are forced to 10b.
00 MCU security status is secure
01 MCU security status is secure
10 MCU security status is unsecure (The standard shipping condition of the flash memory module is
unsecure.)
11 MCU security status is secure
28.34.4 Flash Option Register (FTFL_FOPT)
The flash option register allows the MCU to customize its operations by examining the
state of these read-only bits, which are loaded from NVM at reset. The function of the
bits is defined in the device's Chip Configuration details.
All bits in the register are read-only .
Memory Map and Registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
512 Freescale Semiconductor, Inc.