Information

Addresses: ADC0_SC1A is 4003_B000h base + 0h offset = 4003_B000h
ADC0_SC1B is 4003_B000h base + 4h offset = 4003_B004h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
COCO
AIEN DIFF ADCH
W
Reset
0 0 0 1 1 1 1 1
ADCx_SC1n field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
COCO
Conversion complete flag
The COCO flag is a read-only bit that is set each time a conversion is completed when the compare
function is disabled (ACFE=0) and the hardware average function is disabled (AVGE=0). When the
compare function is enabled (ACFE=1), the COCO flag is set upon completion of a conversion only if the
compare result is true. When the hardware average function is enabled (AVGE=1), the COCO flag is set
upon completion of the selected number of conversions (determined by the AVGS bits). The COCO flag in
SC1A is also set at the completion of a Calibration sequence. The COCO bit is cleared when the
respective SC1n register is written or when the respective Rn register is read.
0 Conversion not completed.
1 Conversion completed.
6
AIEN
Interrupt enable
AIEN enables conversion complete interrupts. When COCO becomes set while the respective AIEN is
high, an interrupt is asserted.
0 Conversion complete interrupt disabled.
1 Conversion complete interrupt enabled.
5
DIFF
Differential mode enable
DIFF configures the ADC to operate in differential mode. When enabled, this mode automatically selects
from the differential channels, and changes the conversion algorithm and the number of cycles to
complete a conversion.
Table continues on the next page...
Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
588 Freescale Semiconductor, Inc.