Information

31.3.2 ADC configuration register 1 (ADCx_CFG1)
CFG1 register selects the mode of operation, clock source, clock divide, and configure
for low power or long sample time.
Addresses: ADC0_CFG1 is 4003_B000h base + 8h offset = 4003_B008h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
ADLPC ADIV ADLSMP MODE ADICLK
W
Reset
0 0 0 0 0 0 0 0
ADCx_CFG1 field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
ADLPC
Low-power configuration
ADLPC controls the power configuration of the successive approximation converter. This optimizes power
consumption when higher sample rates are not required.
0 Normal power configuration.
1 Low power configuration. The power is reduced at the expense of maximum clock speed.
6–5
ADIV
Clock divide select
ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
00 The divide ratio is 1 and the clock rate is input clock.
01 The divide ratio is 2 and the clock rate is (input clock)/2.
10 The divide ratio is 4 and the clock rate is (input clock)/4.
11 The divide ratio is 8 and the clock rate is (input clock)/8.
4
ADLSMP
Sample time configuration
ADLSMP selects between different sample times based on the conversion mode selected. This bit adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion
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Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
590 Freescale Semiconductor, Inc.