Information

ADCx_CFG1 field descriptions (continued)
Field Description
speed for lower impedance inputs. Longer sample times can also be used to lower overall power
consumption if continuous conversions are enabled and high conversion rates are not required. When
ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample
time.
0 Short sample time.
1 Long sample time.
3–2
MODE
Conversion mode selection
MODE bits are used to select the ADC resolution mode.
00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion
with 2's complement output.
01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion
with 2's complement output.
10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion
with 2's complement output.
11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion
with 2's complement output.
1–0
ADICLK
Input clock select
ADICLK bits select the input clock source to generate the internal clock, ADCK. Note that when the
ADACK clock source is selected, it is not required to be active prior to conversion start. When it is
selected and it is not active prior to a conversion start (ADACKEN=0), the asynchronous clock is activated
at the start of a conversion and shuts off when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated.
00 Bus clock.
01 Bus clock divided by 2.
10 Alternate clock (ALTCLK).
11 Asynchronous clock (ADACK).
Chapter 31 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 591