Information

PPB Modules
PPB
ARM Cortex-M4
Core
Debug Interrupts
Crossbar
switch
Figure 3-1. Core configuration
Table 3-1. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M4 core,
r0p1
http://www.arm.com
System memory map System memory map
Clocking Clock distribution
Power management Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
Debug IEEE 1149.1 JTAG
Serial Wire Debug
(SWD)
ARM Real-Time Trace
Interface
Debug
Interrupts Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Private Peripheral Bus
(PPB) module
Miscellaneous Control
Module (MCM)
MCM
3.2.1.1 Buses, interconnects, and interfaces
The ARM Cortex-M4 core has four buses as described in the following table.
Bus name Description
Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is
connected to the crossbar switch via a single master port.
Data code (DCODE) bus
System bus The system bus is connected to a separate master port on the crossbar.
Private peripheral (PPB) bus The PPB provides access to these modules:
• ARM modules such as the NVIC, ITM, DWT, FBP, and ROM table
• Freescale Miscellaneous Control Module (MCM)
Core modules
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
60 Freescale Semiconductor, Inc.