Information

31.3.12 ADC plus-side general calibration value register
(ADCx_CLPS)
For more information, refer to CLPD register description.
Addresses: ADC0_CLPS is 4003_B000h base + 38h offset = 4003_B038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLPS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
ADCx_CLPS field descriptions
Field Description
31–6
Reserved
This read-only field is reserved and always has the value zero.
5–0
CLPS
Calibration value
31.3.13 ADC plus-side general calibration value register
(ADCx_CLP4)
For more information, refer to CLPD register description.
Addresses: ADC0_CLP4 is 4003_B000h base + 3Ch offset = 4003_B03Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP4
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
ADCx_CLP4 field descriptions
Field Description
31–10
Reserved
This read-only field is reserved and always has the value zero.
9–0
CLP4
Calibration value
Chapter 31 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 601