Information

31.3.14 ADC plus-side general calibration value register
(ADCx_CLP3)
For more information, refer to CLPD register description.
Addresses: ADC0_CLP3 is 4003_B000h base + 40h offset = 4003_B040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP3
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
ADCx_CLP3 field descriptions
Field Description
31–9
Reserved
This read-only field is reserved and always has the value zero.
8–0
CLP3
Calibration value
31.3.15 ADC plus-side general calibration value register
(ADCx_CLP2)
For more information, refer to CLPD register description.
Addresses: ADC0_CLP2 is 4003_B000h base + 44h offset = 4003_B044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLP2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
ADCx_CLP2 field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7–0
CLP2
Calibration value
Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
602 Freescale Semiconductor, Inc.