Information

31.3.22 ADC minus-side general calibration value register
(ADCx_CLM2)
For more information, refer to CLMD register description.
Addresses: ADC0_CLM2 is 4003_B000h base + 64h offset = 4003_B064h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
ADCx_CLM2 field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7–0
CLM2
Calibration value
31.3.23 ADC minus-side general calibration value register
(ADCx_CLM1)
For more information, refer to CLMD register description.
Addresses: ADC0_CLM1 is 4003_B000h base + 68h offset = 4003_B068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
ADCx_CLM1 field descriptions
Field Description
31–7
Reserved
This read-only field is reserved and always has the value zero.
6–0
CLM1
Calibration value
Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
606 Freescale Semiconductor, Inc.