Information

are selected using the REFSEL bits in the SC2 register. The alternate (V
ALTH
and V
ALTL
)
voltage reference pair may select additional external pins or internal sources depending
on MCU configuration. Refer to the Chip Configuration information on the Voltage
References specific to this MCU.
In some packages, the external or alternate pairs are connected in the package to V
DDA
and V
SSA
, respectively. One of these positive references may be shared on the same pin
as V
DDA
on some devices. One of these ground references may be shared on the same pin
as V
SSA
on some devices.
If externally available, the positive reference may be connected to the same potential as
V
DDA
or may be driven by an external source to a level between the minimum Ref
Voltage High and the V
DDA
potential (the positive reference must never exceed V
DDA
). If
externally available, the ground reference must be connected to the same voltage
potential as V
SSA
. The voltage reference pairs must be routed carefully for maximum
noise immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array
at each successive approximation step is drawn through the V
REFH
and V
REFL
loop. The
best external component to meet this current demand is a 0.1 μF capacitor with good high
frequency characteristics. This capacitor is connected between V
REFH
and V
REFL
and
must be placed as near as possible to the package pins. Resistance in the path is not
recommended because the current causes a voltage drop that could result in conversion
errors. Inductance in this path must be minimum (parasitic only).
31.6.1.3 Analog input pins
The external analog inputs are typically shared with digital I/O pins on MCU devices.
Empirical data shows that capacitors on the analog inputs improve performance in the
presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with
good high-frequency characteristics is sufficient. These capacitors are not necessary in all
cases, but when used they must be placed as near as possible to the package pins and be
referenced to V
SSA
.
For proper conversion, the input voltage must fall between V
REFH
and V
REFL
. If the input
is equal to or exceeds V
REFH
, the converter circuit converts the signal to 0xFFF (full scale
12-bit representation), 0x3FF (full scale 10-bit representation) or 0xFF (full scale 8-bit
representation). If the input is equal to or less than V
REFL
, the converter circuit converts it
to 0x000. Input voltages between V
REFH
and V
REFL
are straight-line linear conversions.
There is a brief current associated with V
REFL
when the sampling capacitor is charging.
Chapter 31 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 627