Information

Table 3-4. Interrupt vector assignments (continued)
Address Vector IRQ
1
NVIC
non-IPR
register
number
2
NVIC
IPR
register
number
3
Source module Source description
0x0000_0064 25 9 0 2 LLWU Low Leakage Wakeup
NOTE: The LLWU interrupt must not
be masked by the interrupt
controller to avoid a scenario
where the system does not fully
exit stop mode on an LLS
recovery
.
0x0000_0068 26 10 0 2 WDOG Both EWM and WDOG interrupt
sources set this IRQ
0x0000_006C 27 11 0 2 I
2
C0 –
0x0000_0070 28 12 0 3 SPI0 Single interrupt vector for all sources
0x0000_0074 29 13 0 3 I
2
S0 Transmit
0x0000_0078 30 14 0 3 I
2
S1 Receive
0x0000_007C 31 15 0 3 UART0 Single interrupt vector for CEA709.1-B
(LON) status sources
0x0000_0080 32 16 0 4 UART0 Single interrupt vector for UART status
sources
0x0000_0084 33 17 0 4 UART0 Single interrupt vector for UART error
sources
0x0000_0088 34 18 0 4 UART1 Single interrupt vector for UART status
sources
0x0000_008C 35 19 0 4 UART1 Single interrupt vector for UART error
sources
0x0000_0090 36 20 0 5 UART2 Single interrupt vector for UART status
sources
0x0000_0094 37 21 0 5 UART2 Single interrupt vector for UART error
sources
0x0000_0098 38 22 0 5 ADC0
0x0000_009C 39 23 0 5 CMP0 —
0x0000_00A0 40 24 0 6 CMP1 —
0x0000_00A4 41 25 0 6 FTM0 —
0x0000_00A8 42 26 0 6 FTM1 —
0x0000_00AC 43 27 0 6 CMT —
0x0000_00B0 44 28 0 7 RTC Alarm interrupt
0x0000_00B4 45 29 0 7 RTC Seconds interrupt
0x0000_00B8 46 30 0 7 PIT Channel 0
Table continues on the next page...
Core modules
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
64 Freescale Semiconductor, Inc.