Information

32.7.2 CMP Control Register 1 (CMPx_CR1)
Addresses: CMP0_CR1 is 4007_3000h base + 1h offset = 4007_3001h
CMP1_CR1 is 4007_3008h base + 1h offset = 4007_3009h
Bit 7 6 5 4 3 2 1 0
Read
SE WE
0
PMODE INV COS OPE EN
Write
Reset
0 0 0 0 0 0 0 0
CMPx_CR1 field descriptions
Field Description
7
SE
Sample Enable
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is
set and WE is cleared. However, avoid writing 1s to both field locations because this "11" case is
reserved and may change in future implementations.
0 Sampling mode is not selected.
1 Sampling mode is selected.
6
WE
Windowing Enable
At any given time, either SE or WE can be set. If a write to this register attempts to set both, then SE is
set and WE is cleared. However, avoid writing 1s to both field locations because this "11" case is
reserved and may change in future implementations.
0 Windowing mode is not selected.
1 Windowing mode is selected.
5
Reserved
This read-only field is reserved and always has the value zero.
4
PMODE
Power Mode Select
See the electrical specifications table in the device Data Sheet for details.
0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay
and lower current consumption.
1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay
and higher current consumption.
3
INV
Comparator INVERT
Allows selection of the polarity of the analog comparator function. It is also driven to the COUT output, on
both the device pin and as SCR[COUT], when OPE=0.
0 Does not invert the comparator output.
1 Inverts the comparator output.
2
COS
Comparator Output Select
0 Set the filtered comparator output (CMPO) to equal COUT.
1 Set the unfiltered comparator output (CMPO) to equal COUTA.
Table continues on the next page...
Memory map/register definitions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
640 Freescale Semiconductor, Inc.