Information

32.7.5 DAC Control Register (CMPx_DACCR)
Addresses: CMP0_DACCR is 4007_3000h base + 4h offset = 4007_3004h
CMP1_DACCR is 4007_3008h base + 4h offset = 4007_300Ch
Bit 7 6 5 4 3 2 1 0
Read
DACEN VRSEL VOSEL
Write
Reset
0 0 0 0 0 0 0 0
CMPx_DACCR field descriptions
Field Description
7
DACEN
DAC Enable
Enables the DAC. When the DAC is disabled, it is powered down to conserve power.
0 DAC is disabled.
1 DAC is enabled.
6
VRSEL
Supply Voltage Reference Source Select
0 V is selected as resistor ladder network supply reference V.
in1in
1 V is selected as resistor ladder network supply reference V.
in2in
5–0
VOSEL
DAC Output Voltage Select
Selects an output voltage from one of 64 distinct levels.
DACO = (V
in
/64) * (VOSEL[5:0] + 1) , so the DACO range is from V
in
/64 to V
in
.
32.7.6 MUX Control Register (CMPx_MUXCR)
Addresses: CMP0_MUXCR is 4007_3000h base + 5h offset = 4007_3005h
CMP1_MUXCR is 4007_3008h base + 5h offset = 4007_300Dh
Bit 7 6 5 4 3 2 1 0
Read 0
PSEL MSEL
Write
Reset
0 0 0 0 0 0 0 0
CMPx_MUXCR field descriptions
Field Description
7–6
Reserved
This read-only field is reserved and always has the value zero.
5–3
PSEL
Plus Input Mux Control
Determines which input is selected for the plus input of the comparator. For INx inputs, see CMP, DAC,
and ANMUX block diagrams.
Table continues on the next page...
Chapter 32 Comparator (CMP)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 643