Information

32.8.1.2 Continuous mode (#s 2A & 2B)
IRQ
Internal bus
INP
INM
FILTER_CNT
INV
COUT
COUT
OPE
SE
CMPO to
PAD
COUTA
1
WE
0
SE
CGMUX
COS
FILT_PER
0
+
-
FILT_PER
COS
IER/F CFR/F
WINDOW/SAMPLE
1
0
EN,PMODE,HYSTCTR[1:0]
divided
bus
clock
CMPO
bus clock
To other SOC functions
Polarity
select
Window
control
Filter
block
Interrupt
control
Clock
prescaler
Figure 32-21. Comparator operation in Continuous mode
NOTE
See the chip configuration section for the source of sample/
window input.
The analog comparator block is powered and active. CMPO may be optionally inverted,
but is not subject to external sampling or filtering. Both window control and filter blocks
are completely bypassed. SCR[COUT] is updated continuously. The path from
comparator input pins to output pin is operating in combinational unclocked mode.
COUT and COUTA are identical.
For control configurations which result in disabling the filter block, see the Filter Block
Bypass Logic diagram.
Chapter 32 Comparator (CMP)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 647