Information

32.8.2.2 Stop mode operation
Subject to platform-specific clock restrictions, the MCU is brought out of stop when a
compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE]
is enabled, the comparator output operates as in the normal operating mode and
comparator output is placed onto the external pin. In Stop modes, the comparator can be
operational in both:
• High-Speed (HS) Comparison mode when CR1[PMODE] = 1
• Low-Speed (LS) Comparison mode when CR1[PMODE] = 0
It is recommended to use the LS mode to minimize power consumption.
If stop is exited with a reset, all comparator registers are put into their reset state.
32.8.2.3 Low-Leakage mode operation
When the chip is in Low-Leakage modes:
• The CMP module is partially functional and is limited to Low-Speed mode,
regardless of CR1[PMODE] setting
• Windowed, Sampled, and Filtered modes are not supported
• The CMP output pin is latched and does not reflect the compare output state.
The positive- and negative-input voltage can be supplied from external pins or the DAC
output. The MCU can be brought out of the Low-Leakage mode if a compare event
occurs and the CMP interrupt is enabled. After wakeup from low-leakage modes, the
CMP module is in the reset state except for SCR[CFF] and SCR[CFR].
32.8.3 Startup and operation
A typical startup sequence is as follows.
The time required to stabilize COUT will be the power-on delay of the comparators plus
the largest propagation delay from a selected analog source through the analog
comparator, windowing function and filter. See the Data Sheets for power-on delays of
the comparators. The windowing function has a maximum of one bus clock period delay.
The filter delay is specified in the Low-pass filter.
Chapter 32 Comparator (CMP)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 655