Information

Table 3-5. LPTMR interrupt vector assignment

Address Vector IRQ

NVIC

non-IPR

number

NVIC

IPR

number

Source module Source description

0x0000_00DC 55 39 1 9 Low Power Timer —

1. Indicates the NVIC's interrupt source number.

2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this

value is: IRQ div 32

3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4

• The NVIC registers you would use to configure the interrupt are:

• NVICISER1

• NVICICER1

• NVICISPR1

• NVICICPR1

• NVICIABR1

• NVICIPR9

• To determine the particular IRQ's bitfield location within these particular registers:

• NVICISER1, NVICICER1, NVICISPR1, NVICICPR1, NVICIABR1 bit

location = IRQ mod 32 = 7

• NVICIPR9 bitfield starting location = 8 * (IRQ mod 4) + 4 = 28

Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR9

bitfield range is 28-31

Therefore, the following bitfield locations are used to configure the LPTMR interrupts:

• NVICISER1[7]

• NVICICER1[7]

• NVICISPR1[7]

• NVICICPR1[7]

• NVICIABR1[7]

• NVICIPR9[31:28]

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC)

Configuration

This section summarizes how the module has been configured in the chip. Full

documentation for this module is provided by ARM and can be found at http://

www.arm.com.

Core modules

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

66 Freescale Semiconductor, Inc.