Information

• Bandgap enabled/standby (output buffer disabled)
• Low power buffer mode (output buffer enabled)
• High power buffer mode (output buffer enabled)
• 1.2 V output at room temperature
• Dedicated output pin, VREF_OUT
33.1.3 Modes of Operation
The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The
Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait
(VLPW) and Very Low Power Stop (VLPS). If it is desired to use the VREF regulator in
the very low power modes, the system reference voltage must be enabled in these modes.
Refer to the chip configuration chapter for information on enabling this mode of
operation. Having the VREF regulator enabled does increase current consumption. In
very low power modes it may be desirable to disable the VREF regulator to minimize
current consumption. Note however that the accuracy of the output voltage will be
reduced (by as much as several mVs) when the VREF regulator is not used. .
NOTE
The assignment of module modes to core modes is chip-
specific. For module-to-core mode assignments, see the chapter
that describes how modules are configured.
33.1.4 VREF Signal Descriptions
The following table shows the Voltage Reference signals properties.
Table 33-1. VREF Signal Descriptions
Signal Description I/O
VREF_OUT Internally-generated Voltage Reference output O
NOTE
When the VREF output buffer is disabled, the status of the
VREF_OUT signal is high-impedence.
Chapter 33 Voltage Reference (VREFV1)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 663