Information

Memory Map and Register Definition
VREF memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_4000 VREF Trim Register (VREF_TRM) 8 R/W See section
33.2.1/
664
4007_4001 VREF Status and Control Register (VREF_SC) 8 R/W 00h
33.2.2/
665
33.2.1 VREF Trim Register (VREF_TRM)
This register contains bits that contain the trim data for the Voltage Reference.
Address: VREF_TRM is 4007_4000h base + 0h offset = 4007_4000h
Bit 7 6 5 4 3 2 1 0
Read
Reserved CHOPEN TRIM
Write
Reset
x* 0 x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
VREF_TRM field descriptions
Field Description
7
Reserved
This field is reserved.
6
CHOPEN
Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset
will be minimized.
This bit is set during factory trimming of the VREF voltage. This bit should be written to 1 to achieve the
performance stated in the data sheet.
0 Chop oscillator is disabled.
1 Chop oscillator is enabled.
5–0
TRIM
Trim bits
These bits change the resulting VREF by approximately ± 0.5 mV for each step.
NOTE: Min = minimum and max = maximum voltage reference output. For minimum and maximum
voltage reference output values, refer to the Data Sheet for this chip.
Table continues on the next page...
33.2
Memory Map and Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
664 Freescale Semiconductor, Inc.