Information

Chapter 34
Programmable Delay Block (PDB)
34.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The programmable delay block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing
between ADC conversions and/or DAC updates can be achieved. The PDB can
optionally provides pulse outputs (Pulse-Out's) that are used as the sample window in the
CMP block.
34.1.1 Features
• Up to 15 trigger input sources and software trigger source
• Up to eight configurable PDB channels for ADC hardware trigger
• One PDB channel is associated with one ADC.
• One trigger output for ADC hardware trigger and up to eight pre-trigger outputs
for ADC trigger select per PDB channel
• Trigger outputs can be enabled or disabled independently.
• One 16-bit delay register per pre-trigger output
• Optional bypass of the delay registers of the pre-trigger outputs
• Operation in One-Shot or Continuous modes
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 669