Information

Ch n trigger
PDBCHnDLY0
PDBCHnDLYm
=
Ack 0
Pre-trigger 0
Ch n pre-trigger 0
Ch n pre-trigger m
=
BB[m], TOS[m]
BB[0], TOS[0]
EN[0]
EN[m]
MULT
Ack m
Pre-trigger m
Trigger-In 0
DAC interval trigger x
Sequence Error
Detection
ERR[M - 1:0]
PRESCALER
PDB Counter
PDBCNT
PDBMOD
=
Control
Logic
CONT
Trigger-In 1
Trigger-In 14
SWTRIG
TRIGSEL
DACINTx
DAC Interval
Counter
x
EXTx
DAC ext trigger input x
=
DAC interval trigger x
TOEx
PDBIDLY
=
PDB interrupt
TOEx
=
=
POyDLY2
POyDLY1
Pulse
Generation
Pulse-Out y
PDBPOEN[y]
Pulse-Out y
Figure 34-1. PDB Block Diagram
In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out
y is shown. The PDB enable control logic and the sequence error interrupt logic is not
shown.
Introduction
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
672 Freescale Semiconductor, Inc.