Information

PDB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h
34.3.1/
674
4003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh
34.3.2/
677
4003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h
34.3.3/
677
4003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh
34.3.4/
678
4003_6010 Channel n Control Register 1 (PDB0_CH0C1) 32 R/W 0000_0000h
34.3.5/
678
4003_6014 Channel n Status Register (PDB0_CH0S) 32 w1c 0000_0000h
34.3.6/
679
4003_6018 Channel n Delay 0 Register (PDB0_CH0DLY0) 32 R/W 0000_0000h
34.3.7/
680
4003_601C Channel n Delay 1 Register (PDB0_CH0DLY1) 32 R/W 0000_0000h
34.3.8/
680
4003_6190 Pulse-Out n Enable Register (PDB0_POEN) 32 R/W 0000_0000h
34.3.9/
681
4003_6194 Pulse-Out n Delay Register (PDB0_PO0DLY) 32 R/W 0000_0000h
34.3.10/
681
4003_6198 Pulse-Out n Delay Register (PDB0_PO1DLY) 32 R/W 0000_0000h
34.3.10/
681
34.3.1 Status and Control Register (PDBx_SC)
Addresses: PDB0_SC is 4003_6000h base + 0h offset = 4003_6000h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
LDMOD PDBEIE
0
W
SWTRIG
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
DMAEN PRESCALER TRGSEL
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
PDBEN PDBIF PDBIE
0
MULT CONT LDOK
W
Reset
0 0 0 0 0 0 0 0
Memory Map and Register Definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
674 Freescale Semiconductor, Inc.