Information

PDBx_SC field descriptions (continued)
Field Description
0 PDB operation in One-Shot mode
1 PDB operation in Continuous mode
0
LDOK
Load OK
Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm, DACINTx, and POyDLY with
the values written to their buffers. The MOD, IDLY, CHnDLYm, DACINTx, and POyDLY will take effect
according to the LDMOD.
After 1 is written to LDOK bit, the values in the buffers of above registers are not effective and the buffers
cannot be written until the values in buffers are loaded into their internal registers.
LDOK can be written only when PDBEN is set or it can be written at the same time with PDBEN being
written to 1. It is automatically cleared when the values in buffers are loaded into the internal registers or
the PDBEN is cleared. Writing 0 to it has no effect.
34.3.2 Modulus Register (PDBx_MOD)
Addresses: PDB0_MOD is 4003_6000h base + 4h offset = 4003_6004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MOD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDBx_MOD field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–0
MOD
PDB Modulus.
These bits specify the period of the counter. When the counter reaches this value, it will be reset back to
zero. If the PDB is in Continuous mode, the count begins anew. Reading these bits returns the value of
internal register that is effective for the current cycle of PDB.
34.3.3 Counter Register (PDBx_CNT)
Addresses: PDB0_CNT is 4003_6000h base + 8h offset = 4003_6008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 CNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 34 Programmable Delay Block (PDB)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 677