Information

PDBx_CHnDLY1 field descriptions (continued)
Field Description
15–0
DLY
PDB Channel Delay
These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts
when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective
for the current PDB cycle.
34.3.9 Pulse-Out n Enable Register (PDBx_POEN)
Addresses: PDB0_POEN is 4003_6000h base + 190h offset = 4003_6190h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
POEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POEN field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7–0
POEN
PDB Pulse-Out Enable
These bits enable the pulse output. Only lower Y bits are implemented in this MCU.
0 PDB Pulse-Out disabled
1 PDB Pulse-Out enabled
34.3.10 Pulse-Out n Delay Register (PDBx_PODLY)
Addresses: PDB0_PO0DLY is 4003_6000h base + 194h offset = 4003_6194h
PDB0_PO1DLY is 4003_6000h base + 198h offset = 4003_6198h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLY1 DLY2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnDLY field descriptions
Field Description
31–16
DLY1
PDB Pulse-Out Delay 1
These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter
is equal to the DLY1. Reading these bits returns the value of internal register that is effective for the
current PDB cycle.
Table continues on the next page...
Chapter 34 Programmable Delay Block (PDB)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 681