Information

FTM memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_8030 Channel (n) Value (FTM0_C4V) 32 R/W 0000_0000h
35.3.7/
703
4003_8034 Channel (n) Status And Control (FTM0_C5SC) 32 R/W 0000_0000h
35.3.6/
700
4003_8038 Channel (n) Value (FTM0_C5V) 32 R/W 0000_0000h
35.3.7/
703
4003_803C Channel (n) Status And Control (FTM0_C6SC) 32 R/W 0000_0000h
35.3.6/
700
4003_8040 Channel (n) Value (FTM0_C6V) 32 R/W 0000_0000h
35.3.7/
703
4003_8044 Channel (n) Status And Control (FTM0_C7SC) 32 R/W 0000_0000h
35.3.6/
700
4003_8048 Channel (n) Value (FTM0_C7V) 32 R/W 0000_0000h
35.3.7/
703
4003_804C Counter Initial Value (FTM0_CNTIN) 32 R/W 0000_0000h
35.3.8/
704
4003_8050 Capture And Compare Status (FTM0_STATUS) 32 R/W 0000_0000h
35.3.9/
704
4003_8054 Features Mode Selection (FTM0_MODE) 32 R/W 0000_0004h
35.3.10/
706
4003_8058 Synchronization (FTM0_SYNC) 32 R/W 0000_0000h
35.3.11/
708
4003_805C Initial State For Channels Output (FTM0_OUTINIT) 32 R/W 0000_0000h
35.3.12/
711
4003_8060 Output Mask (FTM0_OUTMASK) 32 R/W 0000_0000h
35.3.13/
712
4003_8064 Function For Linked Channels (FTM0_COMBINE) 32 R/W 0000_0000h
35.3.14/
714
4003_8068 Deadtime Insertion Control (FTM0_DEADTIME) 32 R/W 0000_0000h
35.3.15/
719
4003_806C FTM External Trigger (FTM0_EXTTRIG) 32 R/W 0000_0000h
35.3.16/
720
4003_8070 Channels Polarity (FTM0_POL) 32 R/W 0000_0000h
35.3.17/
722
4003_8074 Fault Mode Status (FTM0_FMS) 32 R/W 0000_0000h
35.3.18/
724
4003_8078 Input Capture Filter Control (FTM0_FILTER) 32 R/W 0000_0000h
35.3.19/
726
4003_807C Fault Control (FTM0_FLTCTRL) 32 R/W 0000_0000h
35.3.20/
727
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
694 Freescale Semiconductor, Inc.