Information

Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be
checked using only one read of STATUS. All CHnF bits can be cleared by reading
STATUS followed by writing 0x00 to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHF is
cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit.
Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF
interrupt request is not lost due to the clearing sequence for a previous CHF.
NOTE
The STATUS register should be used only in Combine mode.
Addresses: FTM0_STATUS is 4003_8000h base + 50h offset = 4003_8050h
FTM1_STATUS is 4003_9000h base + 50h offset = 4003_9050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CH7F CH6F CH5F CH4F CH3F CH2F CH1F CH0F
W 0 0 0 0 0 0 0 0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_STATUS field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
CH7F
Channel 7 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
6
CH6F
Channel 6 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
5
CH5F
Channel 5 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
Table continues on the next page...
Chapter 35 FlexTimer Module (FTM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 705