Information

FTMx_STATUS field descriptions (continued)
Field Description
4
CH4F
Channel 4 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
3
CH3F
Channel 3 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
2
CH2F
Channel 2 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
1
CH1F
Channel 1 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
0
CH0F
Channel 0 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
35.3.10 Features Mode Selection (FTMx_MODE)
This register contains the global enable bit for FTM-specific features and the control bits
used to configure:
• Fault control mode and interrupt
• Capture Test mode
• PWM synchronization
• Write protection
• Channel output initialization
These controls relate to all channels within this module.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
706 Freescale Semiconductor, Inc.